Cache Coherence问题发生的位置: 共享cache和独享cache 的边界。多核系统中，处理器写请求commit的时间: 该写请求被其他所有核确认，注意这个时间和write complete的时间（值被更新到cache line中）并不相同。
1. coherence的定义
A memory system is coherent if:
The results of a parallel program’s execution are such that for each memory location, there is a hypothetical serial order of all program operations (executed by all processors) to the location that is consistent with the results of execution, and:
- Memory operations issues by any one processor occur in the order issued by the processor
- The value returned by a read is the value written by the last write to the location as given by the serial order.
注意: 即使是单处理器系统其实也存在coherence问题，因为各个硬件和处理器共享内存，因此硬件映射内存通常都被设置为not-cachable。
- obeys program order: A read by processor P to address X that follows a write by P to address X, should return the value of the write by P.
- write propagation: A read by processor P1 to address X that follows a write by process P2 to X returns the written value
- write serialization: two writes to address X by any two processors observed in the same order by all processors
true sharing: cache line size增长，locality增长，true sharing的开销被均摊了，因此减少true sharing。
false sharing: cache line size increase, probability of false sharing increases
2. snoopy based coherence protocol
3. VI
3.1. MSI
3.2. MESI
4. directory based coherence protocol
点到点通信
hyperqueue
- one entry per cache line memory
- dirty
- present
- point to point communication
- local node: node where a request originates
- home node: node where the memory location of an address resides
- remote node: node that has a copy of a cache block, whether exclusive or shared
4.1. 优化1: 减小存储空间
- 有限指针
- sparse directory
4.2. 优化2: 减小通信开销
5. implementation of snoopy based cache
5.1. 实现1: 原子总线
5.2. 实现2: transaction-split总线
idea 区分事务请求和响应
- 问题1: 匹配请求和响应
- request table
- 问题2: 处理冲突
- disallow conflicting requests
- each processor has a copy of request table
- 问题3: 流控制
- negative acknowledgement
- 问题4: snoop结果报告的时机
condition1: program order condition2: